View M5M29KB331ATP_5661475.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev.0.1_48a_bezz 1 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory pin configuration (top view) digital cellar phone, telecommunication, pda, car navigation system, video game machine description features access time random 70ns (max.) page 25ns(max.) supply voltage vcc= 3.0 ~ 3.6v ambient temperature ta= - 40 ~ 85 c package 52pin tsop(type - ii), lead pitch 0.4mm outer - lead finishing : sn - cu application vcc : vcc gnd : gnd a0 - a20 : address dq0 - dq15 : data i/o ce# : chip enable oe# : output enable we# : write enable wp# : write protect rp# : reset power down byte# : byte enable m5m29kb/t331atp the m5m29kb/t331atp are 3.3v - only high speed 33,554,432 - bit cmos boot block flash memories with alternating bgo(back ground operation) feature. the bgo feature of the device allows program or erase operations to be performed in one bank while the device simultaneously allows read operations to be performed on the other bank. this bgo feature is suitable for mobile and personal computing, and communication products. the m5m29kb/t331atp are fabricated by cmos technology for the peripheral circuit and dinor iv(divided bit - line nor iv) architecture for the memory cell, and are available in a 52 - pin tsop(ii) for lead free use. m5m29kb/t331atp provides for software lock release function. usually, all memory blocks are locked and can not be programmed or erased, when wp# is low. using software lock release function, program or erase operation can be executed. outline 52ptg - a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we # rp # wp # nc nc a20 a18 a17 a7 a6 a5 a4 a3 a16 nc gnd nc dq15/a - 1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe # gnd 28 27 a0 25 26 a2 a1 10.49 mm 10.79 mm nc byte# ce #
rev.0.1_48a_bezz 2 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory capacitance 32 m flash memory block diagram a0 to a20 oe# we# wp# rp# dq0 to dq15 32 mbit dinor iv flash memory vcc gnd ce# byte# min. typ. max. cin input capacitance a20-a0, oe#, we#, ce#, wp#, rp#,byte# 12 pf cout output capacitance dq15-dq0 12 pf symbol conditions ta=25c, f=1mhz, vin=vout=0v unit limits parameter
rev.0.1_48a_bezz 3 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory the 32m - bit dinor iv(divided bit line nor iv) flash memory is 3.3v - only high speed 33,554,432 - bit cmos boot block flash memory. alternating bgo(back ground operation) feature of the device allows program or erase operations to be performed in one bank while the device simultaneously allows read operations to be performed on the other bank. this bgo feature is suitable for communication products and cellular phone.the flash memory is fabricated by cmos technology for the peripheral circuits and dinor iv architecture for the memory cells. features - organization 2,097,152 - word x 16 - bit 4,194,304 - byte x 8 - bit - supply voltage vcc = 3.0 ~ 3.6v - access time random access 70ns(max.) random page read 25ns(max.) - read 108mw (max. at 5mhz) - page read 36mw (max.) (after automatic power down) 0.33 w(typ.) - program/erase 126mw(max.) standby 0. 33 w(typ.) deep power down mode 0. 33 w(typ.) - auto program for bank(i) ? bank(iv) program time word program 30 s/word(typ.) byte program 30 s/byte(typ.) page program 4ms(typ.) program unit word/byte program 1word/ 1byte page program 128 words/ 256 bytes - auto erase erase time main block 150ms/block (typ.) erase unit bank(i) boot block 4k - word x2/ 8k - byte x2 parameter block 4k - word x6 / 8k - byte x6 main block 32k - word x7 / 64k - byte x7 bank(ii) main block 32k - word x8 / 64k - byte x8 bank(iii) main block 32k - word x24 / 64k - byte x24 bank(iv) main block 32k - word x24 / 64k - byte x24 - program/erase cycles 100kcycles - boot block bottom boot m***b33****** top boot m***t33****** - the other functions software command control software lock release(while wp# is low) erase suspend/resume program suspend/resume status register read alternating back ground program/erase operation between bank(i), bank(ii), bank(iii) and bank(iv) random page read flash memory part description
rev.0.1_48a_bezz 4 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory block diagram (32mbit flash memory) main block 70 32k-word bank(iv) 24 blocks main block 47 32k-word main block 46 32k-word bank(iii) 24 blocks main block 23 32k-word main block 22 32k-word bank(ii) 8 blocks main block 15 32k-word main block 14 32k-word main block 8 32k-word bank(i) parameter block 7 4k-word 15 blocks parameter block 2 4k-word boot block 1 4k-word boot block 0 4k-word data i/o command user interface status / id register multiplexer write state machine i/o buffer 128-word page buffer y-decoder y-gate / sense amp. address input x-decoder a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ce# oe# we# wp# rp# dq0 dq1 dq15 /a-1 dq14 vcc gnd chip enable output enable write enable write protect reset / powerdown byte# byte enable
rev.0.1_48a_bezz 5 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory when rp# is at vil, the device is in the deep power down mode and its power consumption is substantially low. during read modes, the memory is deselected and the data input/output are in a high - impedance (high - z) state. after return from power down, the cui is reset to read array, and the status register is cleared to value 80h. during block erase or program modes, rp# low will abort either operation. memory array data of the block being altered become invalid. the automatic power down minimizes the power consumption during read mode. the device automatically turns to this mode when any addresses or ce# isn't changed more than 200ns after the last alternation. the power consumption becomes the same as the stand - by mode. during this mode, the output data is latched and can be read out. new data is read out correctly when addresses are changed. in the 32m - bit dinor iv flash memory , when one memory address is read according to a read mode in the case of the same as an access when a read mode command is input, an another bank memory data can be read out (random or page mode) by changing an another bank address. when oe# is at vih, output from the devices is disabled. data input/output are in a high - impedance (high - z) state. output disable the 32m - bit dinor iv flash memory includes on - chip program/erase control circuitry. the write state machine (wsm) controls block erase and word/page program operations. operational modes are selected by the commands written to the command user interface (cui). the status register indicates the status of the wsm and when the wsm successfully completes the desired program or block erase operation. a deep power down mode is enabled when the rp# pin is at gnd, minimizing power consumption. function of flash memory the 32m - bit dinor iv flash memory has four read modes, which accesses to the memory array, the page read, the device identifier and the status register. the appropriate read commands are required to be written to the cui. upon initial device power up or after exit from deep power down, the 32m - bit dinor iv flash memory automatically resets to read array mode. in the read array mode and in the conditions are low level input to oe#, high level input to we# and rp#, low level input to ce# and address signals to the address inputs (a20 - a0: word mode / a20 - a - 1: byte mode) the data of the addressed location to the data input/output (dq15 - dq0: word mode / dq7 - dq0: byte mode) is output. read writes to the cui enables reading of memory array data, device identifiers and reading and clearing of the status register. they also enable block erase and program. the cui is written by bringing we# to low level and oe# is at high level, while ce# is at low level. address and data are latched on the earlier rising edge of we# and ce#. standard micro processor write timings are used. write the 32m - bit dinor iv flash memory allows to read array from one bank while the other bank operates in software command write cycling or the erasing / programming operation in the background. array read operation with the other bank in bgo is performed by changing the bank address without any additional command. when the bank address points the bank in software command write cycling or the erasing / programming operation, the data is read out from the status register. the access time with bgo is the same as the normal read operation. bgo must be between bank(i), bank(ii), bank(iii) and bank(iv). when ce# is at vih, the device is in the standby mode and its power consumption is reduced. data input/output are in a high - impedance (high - z) state. if the memory is deselected during block erase or program, the internal control circuits remain active and the device consumes normal active power until the operation completes. standby alternating background operation (bgo) read deep power down bbr(back bank array read) automatic power down (auto - pd)
rev.0.1_48a_bezz 6 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory we can normally read device identifier codes when read device identifier code command (90h) is written to the command latch. following the command write, the manufacturer code and the device code can be read from a0 address 0h and 1h in a bank address, respectively. the device is in read array mode on initial device power up and after exit from deep power down, or by writing ffh to the command user interface. after starting the internal operation the device is set to the read status register mode automatically. automated block erase is initiated by writing the block erase command of 20h followed by the confirm command of d0h. an address within the block to be erased is required. the wsm executes iterative erase pulse application and erase verify operation. word / byte program is executed by a two - command sequence. the word/byte program setup command of 40h is written to the command interface, followed by a second write specifying the address and data to be written. the wsm controls the program pulse application and verify operation. page program allows fast programming of 128 words/ 256 bytes of data. writing of 41h initiates the page program operation for the data area. from 2nd cycle to 129th cycle(word mode)/ 257th cycle(byte mode), write data must be serially inputted. address a6 - a0(word mode)/ a6 - a - 1(byte mode) have to be incremented from 00h to 7fh. after completion of data loading, the wsm controls the program pulse application and verify operation. single data load to the page buffer is performed by writing 74h followed by a second write specifying the column address (a6 to a0 or a6 to a - 1) and data. distinct data up to 128word can be loaded to the page buffer by this two - command sequence. on the other hand, all of the loaded data to the page buffer is programmed simultaneously by writing page buffer to flash command of 0eh followed by the confirm command of d0h. after completion of programming the data on the page buffer is cleared automatically. the device operations are selected by writing specific software command into the command user interface. software command definitions the status register is read after writing the read status register command of 70h to the command user interface. also, after starting the internal operation the device is set to the read status register mode automatically. the contents of status register are latched on the later falling edge of oe# or ce#. when status read is required, oe# or ce# must be toggled every status read. the erase status, program status and block status bits are set to "1"s by the write state machine and can only be reset by the clear status register command of 50h. these bits indicate various failure conditions. a) word / byte program (40h) program commands block erase / confirm command (20h/d0h) clear status register command (50h) read array command (ffh) read status register command (70h) read device identifier command (90h) page read command (f3h) b) page program for data blocks (41h) c) single data load to page buffer (74h) / page buffer to flash (0eh/d0h) the page read command (f3h) timing can be used by writing the first command and ce# falls vil or changing the address(a20 - a2) is necessary to start activating page read mode. this command is fast random 4 words read. during the read cycle operation it is necessary to fix ce# low and change addresses which are defined by a0 and a1(or a - 1 to a1) at random continuously. the mode is kept until rp# is set to vil or this chip is powered down. the first read of page read timing is the same as normal read (ta(ce)). ce# should be fallen vil. the read timing after the first is fast read (ta(pad)). in the page read mode the upper address(a20 - a2) is supposed not to be clocked during read operation. otherwise the access time is as same as normal read.
rev.0.1_48a_bezz 7 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory loaded data to the page buffer is cleared by writing the clear page buffer command of 55h followed by the confirm command of d0h. this command is valid for clearing data loaded by single data load to page buffer command. writing the suspend command of b0h during block erase operation interrupts the block erase operation and allows read out from another block of memory. writing the suspend command of b0h during program operation interrupts the program operation and allows read out from another block of memory. the bank address is required when writing the suspend/resume command. the device continues to output status register data when read, after the suspend command is written to it. polling the wsm status and suspend status bits will determine when the erase operation or program operation has been suspended. at this point, writing of the read array command to the cui enables reading data from blocks other than that which is suspended. when the resume command of d0h is written to the cui, the wsm will continue with the erase or program processes. the 32m - bit dinor iv flash memory has a master write protect pin (wp#). when wp# is at vih, all blocks can be programmed or erased. when wp# is low, all blocks are in locked mode which prevents any modifications to memory blocks. software lock release function is only command which allows to program or erase. when the power supply voltage is less than vlko, low vcc lock - out voltage, the device is set to the read - only mode. a delay time of 2 s is required before any device operation is initiated. the delay time is measured from the time flash vcc reaches flash vccmin (3.0v). during power up, rp# = gnd is recommended. falling in busy status is not recommended for possibility of damaging the device. array data load to the page buffer is performed by writing the flash to page buffer command of f1h followed by the confirm command of d0h. an address within the page to be loaded is required. then the array data can be copied into the other pages within the same bank by using the page buffer to flash command. flash to page buffer command (f1h/d0h) the 32m - bit dinor iv flash memory is constructed by 2 boot blocks of 4k words/ 8k bytes, 6 parameter blocks of 4k words/ 8k bytes and 7 main blocks of 32k words/ 64k bytes in bank(i), by 8 main blocks of 32k words/ 64k bytes in bank(ii) and by 24 main blocks of 32k words/ 64k bytes in bank(iii) and bank(iv). power supply voltage clear page buffer command (55h/d0h) data protection suspend/resume command (b0h/d0h) memory organization the command sequence enable us to erase all blocks. the command can be used by writing setup command a7h(1 st cycle) and confirm command d0h(2 nd cycle). the sequence is not valid in case of wp#=vil. erase all unlocked blocks command (a7h/d0h)
rev.0.1_48a_bezz 8 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory block organization 32 m - bit dinor(iv) flash memory map (bottom boot) x8 (byte mode) x16 (word mode) x8 (byte mode) x16 (word mode) 1b0000h- 1bffffh d8000h- dffffh 32kword main block 34 3f0000h- 3fffffh 1f8000h- 1fffffh 32kword main block 70 1a0000h- 1affffh d0000h- d7fffh 32kword main block 33 3e0000h- 3effffh 1f0000h- 1f7fffh 32kword main block 69 190000h- 19ffffh c8000h- cffffh 32kword main block 32 3d0000h- 3dffffh 1e8000h- 1effffh 32kword main block 68 180000h- 18ffffh c0000h- c7fffh 32kword main block 31 3c0000h- 3cffffh 1e0000h- 1e7fffh 32kword main block 67 170000h- 17ffffh b8000h- bffffh 32kword main block 30 3b0000h- 3bffffh 1d8000h- 1dffffh 32kword main block 66 160000h- 16ffffh b0000h- b7fffh 32kword main block 29 3a0000h- 3affffh 1d0000h- 1d7fffh 32kword main block 65 150000h- 15ffffh a8000h- affffh 32kword main block 28 390000h- 39ffffh 1c8000h- 1cffffh 32kword main block 64 140000h- 14ffffh a0000h- a7fffh 32kword main block 27 380000h- 38ffffh 1c0000h- 1c7fffh 32kword main block 63 130000h- 13ffffh 98000h- 9ffffh 32kword main block 26 370000h- 37ffffh 1b8000h- 1bffffh 32kword main block 62 120000h- 12ffffh 90000h- 97fffh 32kword main block 25 360000h- 36ffffh 1b0000h- 1b7fffh 32kword main block 61 110000h- 11ffffh 88000h- 8ffffh 32kword main block 24 350000h- 35ffffh 1a8000h- 1affffh 32kword main block 60 100000h- 10ffffh 80000h- 87fffh 32kword main block 23 340000h- 34ffffh 1a0000h- 1a7fffh 32kword main block 59 f0000h- fffffh 78000h- 7ffffh 32kword main block 22 330000h- 33ffffh 198000h- 19ffffh 32kword main block 58 e0000h- effffh 70000h- 77fffh 32kword main block 21 320000h- 32ffffh 190000h- 197fffh 32kword main block 57 d0000h- dffffh 68000h- 6ffffh 32kword main block 20 310000h- 31ffffh 188000h- 18ffffh 32kword main block 56 c0000h- cffffh 60000h- 67fffh 32kword main block 19 300000h- 30ffffh 180000h- 187fffh 32kword main block 55 b0000h- bffffh 58000h- 5ffffh 32kword main block 18 2f0000h- 2fffffh 178000h- 17ffffh 32kword main block 54 a0000h- affffh 50000h- 57fffh 32kword main block 17 2e0000h- 2effffh 170000h- 177fffh 32kword main block 53 90000h- 9ffffh 48000h- 4ffffh 32kword main block 16 2d0000h- 2dffffh 168000h- 16ffffh 32kword main block 52 80000h- 8ffffh 40000h- 47fffh 32kword main block 15 2c0000h- 2cffffh 160000h- 167fffh 32kword main block 51 70000h- 7ffffh 38000h- 3ffffh 32kword main block 14 2b0000h- 2bffffh 158000h- 15ffffh 32kword main block 50 60000h- 6ffffh 30000h- 37fffh 32kword main block 13 2a0000h- 2affffh 150000h- 157fffh 32kword main block 49 50000h- 5ffffh 28000h- 2ffffh 32kword main block 12 290000h- 29ffffh 148000h- 14ffffh 32kword main block 48 40000h- 4ffffh 20000h- 27fffh 32kword main block 11 280000h- 28ffffh 140000h- 147fffh 32kword main block 47 30000h- 3ffffh 18000h- 1ffffh 32kword main block 10 270000h- 27ffffh 138000h- 13ffffh 32kword main block 46 20000h- 2ffffh 10000h- 17fffh 32kword main block 9 260000h- 26ffffh 130000h- 137fffh 32kword main block 45 10000h- 1ffffh 08000h- 0ffffh 32kword main block 8 250000h- 25ffffh 128000h- 12ffffh 32kword main block 44 0e000h- 0ffffh 07000h- 07fffh 4kword parameter block 7 240000h- 24ffffh 120000h- 127fffh 32kword main block 43 0c000h- 0dfffh 06000h- 06fffh 4kword parameter block 6 230000h- 23ffffh 118000h- 11ffffh 32kword main block 42 0a000h- 0bfffh 05000h- 05fffh 4kword parameter block 5 220000h- 22ffffh 110000h- 117fffh 32kword main block 41 08000h- 09fffh 04000h- 04fffh 4kword parameter block 4 210000h- 21ffffh 108000h- 10ffffh 32kword main block 40 06000h- 07fffh 03000h- 03fffh 4kword parameter block 3 200000h- 20ffffh 100000h- 107fffh 32kword main block 39 04000h- 05fffh 02000h- 02fffh 4kword parameter block 2 1f0000h- 1fffffh f8000h- fffffh 32kword main block 38 02000h- 03fffh 01000h- 01fffh 4kword boot block 1 1e0000h- 1effffh f0000h- f7fffh 32kword main block 37 00000h- 01fffh 00000h- 00fffh 4kword boot block 0 1d0000h- 1dffffh e8000h- effffh 32kword main block 36 a20-a-1 (byte mode) a20-a0 (word mode) 1c0000h- 1cffffh e0000h- e7fffh 32kword main block 35 a20-a-1 (byte mode) a20-a0 (word mode) bank(iii) bank(i) bank(ii) bank(iii) bank(iv)
rev.0.1_48a_bezz 9 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory block organization 32 m - bit dinor(iv) flash memory map (top boot) x8 (byte mode) x16 (word mode) x8 (byte mode) x16 (word mode) 230000h- 23ffffh 118000h- 11ffffh 32kword main block 35 3fe000h- 3fffffh 1ff000h- 1fffffh 4kword boot block 70 220000h- 22ffffh 110000h- 117fffh 32kword main block 34 3fc000h- 3fdfffh 1fe000h- 1fefffh 4kword boot block 69 210000h- 21ffffh 108000h- 10ffffh 32kword main block 33 3fa000h- 3fbfffh 1fd000h- 1fdfffh 4kword parameter block 68 200000h- 20ffffh 100000h- 107fffh 32kword main block 32 3f8000h- 3f9fffh 1fc000h- 1fcfffh 4kword parameter block 67 1f0000h- 1fffffh f8000h- fffffh 32kword main block 31 3f6000h- 3f7fffh 1fb000h- 1fbfffh 4kword parameter block 66 1e0000h- 1effffh f0000h- f7fffh 32kword main block 30 3f4000h- 3f5fffh 1fa000h- 1fafffh 4kword parameter block 65 1d0000h- 1dffffh e8000h- effffh 32kword main block 29 3f2000h- 3f3fffh 1f9000h- 1f9fffh 4kword parameter block 64 1c0000h- 1cffffh e0000h- e7fffh 32kword main block 28 3f0000h- 3f1fffh 1f8000h- 1f8fffh 4kword parameter block 63 1b0000h- 1bffffh d8000h- dffffh 32kword main block 27 3e0000h- 3effffh 1f0000h- 1f7fffh 32kword main block 62 1a0000h- 1affffh d0000h- d7fffh 32kword main block 26 3d0000h- 3dffffh 1e8000h- 1effffh 32kword main block 61 190000h- 19ffffh c8000h- cffffh 32kword main block 25 3c0000h- 3cffffh 1e0000h- 1e7fffh 32kword main block 60 180000h- 18ffffh c0000h- c7fffh 32kword main block 24 3b0000h- 3bffffh 1d8000h- 1dffffh 32kword main block 59 170000h- 17ffffh b8000h- bffffh 32kword main block 23 3a0000h- 3affffh 1d0000h- 1d7fffh 32kword main block 58 160000h- 16ffffh b0000h- b7fffh 32kword main block 22 390000h- 39ffffh 1c8000h- 1cffffh 32kword main block 57 150000h- 15ffffh a8000h- affffh 32kword main block 21 380000h- 38ffffh 1c0000h- 1c7fffh 32kword main block 56 140000h- 14ffffh a0000h- a7fffh 32kword main block 20 370000h- 37ffffh 1b8000h- 1bffffh 32kword main block 55 130000h- 13ffffh 98000h- 9ffffh 32kword main block 19 360000h- 36ffffh 1b0000h- 1b7fffh 32kword main block 54 120000h- 12ffffh 90000h- 97fffh 32kword main block 18 350000h- 35ffffh 1a8000h- 1affffh 32kword main block 53 110000h- 11ffffh 88000h- 8ffffh 32kword main block 17 340000h- 34ffffh 1a0000h- 1a7fffh 32kword main block 52 100000h- 10ffffh 80000h- 87fffh 32kword main block16 330000h- 33ffffh 198000h- 19ffffh 32kword main block 51 f0000h- fffffh 78000h- 7ffffh 32kword main block 15 320000h- 32ffffh 190000h- 197fffh 32kword main block 50 e0000h- effffh 70000h- 77fffh 32kword main block 14 310000h- 31ffffh 188000h- 18ffffh 32kword main block 49 d0000h- dffffh 68000h- 6ffffh 32kword main block 13 300000h- 30ffffh 180000h- 187fffh 32kword main block 48 c0000h- cffffh 60000h- 67fffh 32kword main block 12 2f0000h- 2fffffh 178000h- 17ffffh 32kword main block 47 b0000h- bffffh 58000h- 5ffffh 32kword main block 11 2e0000h- 2effffh 170000h- 177fffh 32kword main block46 a0000h- affffh 50000h- 57fffh 32kword main block 10 2d0000h- 2dffffh 168000h- 16ffffh 32kword main block 45 90000h- 9ffffh 48000h- 4ffffh 32kword main block 9 2c0000h- 2cffffh 160000h- 167fffh 32kword main block 44 80000h- 8ffffh 40000h- 47fffh 32kword main block 8 2b0000h- 2bffffh 158000h- 15ffffh 32kword main block 43 70000h- 7ffffh 38000h- 3ffffh 32kword main block 7 2a0000h- 2affffh 150000h- 157fffh 32kword main block 42 60000h- 6ffffh 30000h- 37fffh 32kword main block 6 290000h- 29ffffh 148000h- 14ffffh 32kword main block 41 50000h- 5ffffh 28000h- 2ffffh 32kword main block 5 280000h- 28ffffh 140000h- 147fffh 32kword main block 40 40000h- 4ffffh 20000h- 27fffh 32kword main block 4 270000h- 27ffffh 138000h- 13ffffh 32kword main block 39 30000h- 3ffffh 18000h- 1ffffh 32kword main block 3 260000h- 26ffffh 130000h- 137fffh 32kword main block 38 20000h- 2ffffh 10000h- 17fffh 32kword main block 2 250000h- 25ffffh 128000h- 12ffffh 32kword main block 37 10000h- 1ffffh 08000h- 0ffffh 32kword main block 1 240000h- 24ffffh 120000h- 127fffh 32kword main block 36 00000h- 0ffffh 00000h- 07fffh 32kword main block 0 a20-a-1 (byte mode) a20-a0 (word mode) a20-a-1 (byte mode) a20-a0 (word mode) bank(iv) bank(iii) bank(ii) bank(i) bank(iii)
rev.0.1_48a_bezz 10 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory bus operation ce# oe# we# rp# dq0-15 array vil vil vih vih data output page vil vil vih vih data output status register vil vil vih vih status register data identifier code vil vil vih vih identifier code output disable vil vih vih vih high-z program vil vih vil vih command/data in erase vil vih vil vih command others vil vih vil vih command vih x 1) x 1) vih high-z x 1) x 1) x 1) vil high-z deep power down read write stand by mode pins byte#=vih 1 ) x can be vih or vil for control pins. ce# oe# we# rp# dq0-7 array vil vil vih vih data output page vil vil vih vih data output status register vil vil vih vih status register data identifier code vil vil vih vih identifier code output disable vil vih vih vih high-z program vil vih vil vih command/data in erase vil vih vil vih command others vil vih vil vih command vih x 1) x 1) vih high-z x 1) x 1) x 1) vil high-z deep power down read write stand by mode pins byte#=vil
rev.0.1_48a_bezz 11 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory software command definition command list (wp# =vih or vil) 1) in the case of word mode(byte#=vih), upper byte data (dq15 - dq8) is ignored. 2) bank=bank address (bank(i) - bank(iv): a20 - 18) 3) ia=id code address: a0=vil (manufacturer ? s code): a0=vih (device code), id=id code 4) srd=status register data 5) sa=a20 - a2: page address, a1, a0(a1 - a - 1):voluntary address / rd0=1 st page read data 6) sa+i: page address(is equal to 1 st page address of a20 - a2), a1,a0(a1 - a - 1): voluntary address / rdi : 2 nd page read data command list (wp# =vih) data 1) data data (dq0-15),(dq0-7) a20-a18 a0 (dq0-15),(dq0-7) (dq0-15),(dq0-7) read array write x ffh page read write x f3h read rd0 5) read sa+i 6) rdi 6) device identifier write bank 2) 90h read bank 2) ia 3) id 3) read status register write bank 2) 70h read srd 4) clear status register write x 50h suspend write bank 2) b0h resume write bank 2) d0h sa 5) bank 2) command 1st bus cycle mode address 2nd bus cycle 3rd-5th bus cycles (word mode) 3rd-9th bus cycles (byte mode) mode address mode address data 1) data 1) data 1) (dq0-15),(dq0-7) (dq0-15),(dq0-7) (dq0-15),(dq0-7) word program write bank 2) 40h write wa 3) wd 3) page program write bank 2) 41h write wa0 4) wd0 4) write wan 4) wdn 4) page buffer to flash write bank 2) 0eh write wa 5) d0h 1) block erase/confirm write bank 2) 20h write ba 6) d0h 1) erase all unlocked blocks write x a7h write x d0h 1) clear page buffer write x 55h write x d0h 1) single data load to page buffer write bank 2) 74h write wa 3) wd 3) flash to page buffer write bank 2) f1h write ra 7) d0h 1) 2nd bus cycle mode address 3rd-129th bus cycles (word mode) 3rd-257th bus cycles (byte mode) mode address command 1st bus cycle mode address 1) in the case of word mode(byte#=vih),upper byte data (dq15 - dq8) is ignored. 2) bank=bank address (bank(i) - bank(iv): a20 - a18) 3) wa=write address, wd=write data 4) wa0, wan=write address, wd0, wdn=write data. word mode (byte#=vih) : write address and write data must be provided sequentially fr om 00h to 7fh for a6 - a0. page size is 128 words (128 - word x 16 - bit), and also a20 - a7 (block address, page address) must be valid. byte mode (byte#=vil) : write address and write data must be provided sequentially fr om 00h to ffh for a6 - a - 1. page size is 256 bytes (256 - byte x 8 - bit), and also a20 - a7 (block address, page address) must be valid. 5) wa=write address: a20 - a7 (block address, page address) must be valid. 6) ba=block address : a20 - a12[bank(i)], a20 - a15 [bank(ii), bank(iii), bank(iv)] must be valid. 7) ra=read address: a20 - a7 (block address, page address) must be valid.
rev.0.1_48a_bezz 12 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory data 1) data 1) data 1) (dq0-15/dq0-7) (dq0-15/dq0-7) (dq0-15/dq0-7) word/byte program write bank 60h write bank block 6) write bank ach page program write bank 60h write bank block 6) write bank ach page buffer to flash write bank 60h write bank block 6) write bank ach block erase/confirm write bank 60h write bank block 6) write bank ach clear page buffer write bank 60h write bank block 6) write bank ach single data load to page buffer write bank 60h write bank block 6) write bank ach flash to page buffer write bank 60h write bank block 6) write bank ach data 1) data 1) (dq0-15/dq0-7) (dq0-15/dq0-7) word/byte program write bank block# 6) write bank 7bh page program write bank block# 6) write bank 7bh page buffer to flash write bank block# 6) write bank 7bh block erase/confirm write bank block# 6) write bank 7bh clear page buffer write bank block# 6) write bank 7bh single data load to page buffer write bank block# 6) write bank 7bh flash to page buffer write bank block# 6) write bank 7bh data 1) data data (dq0-15/dq0-7) (dq0-15/dq0-7) (dq0-15/dq0-7) word/byte program write bank 40h write wa 2) wd 2) page program write bank 41h write wa0 3) wd0 3) write wan 3) wdn 3) page buffer to flash write bank 0eh write wa 4) d0h 1) block erase/confirm write bank 20h write ba 5) d0h 1) clear page buffer write x 55h write x d0h 1) single data load to page buffer write bank 74h write wa 2) wd 2) flash to page buffer write bank f1h write ra 7) d0h 1) 8th-134th bus cycles(word mode) 8th-262th bus cycles(byte mode) mode address mode address mode address setup command for software lock release setup command for program or erase operations 6th bus cycle 7th bus cycle setup command for software lock release 4th bus cycle 5th bus cycle mode address mode address 3rd bus cycle mode address mode address 1st bus cycle mode address 2nd bus cycle 7) ra=read address: a20 - a7 (block address, page address) must be valid. command list (wp# =vil) software command definition software lock release operation needs following consecutive 7bus cycles.moreover, additional 127(255) bus cycles are needed for page program operation. address dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 block fixed 0 fixed 0 a20 a19 a18 a17 a16 a15 block# fixed 0 fixed 0 a20# a19# a18# a17# a16# a15# 1 ) in the case of word mode(byte#=vih) upper byte data (dq15 - dq8) is ignored. 2) wa=write address, wd=write data 3) wa0, wan=write address, wd0, wdn=write data. write address an d write data must be provided sequentially from 00h to 7fh for a6 - a0(word mode) and from 00h to ffh for a6 - a - 1(byte mode), respectively. page size is 128 words (128 - word x 16 - bit/ word mode) or page size is 256 bytes (256 - word x 8 - bit/ byte mode), and also a20 - a7 (block address, page address) must be valid. 4) wa=write address: a20 - a7 (block address, page address) must be valid. 5) ba=block address : a20 - a12[bank(i)], a20 - a15 [bank(ii), bank(iii), bank(iv)] 6) block=block address: a20 - a15, block#=a20# - a15# must be valid.
rev.0.1_48a_bezz 13 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory block locking wp# pin must not be switched during performing read / write oper ations or wsm busy (wsms=0). status register bank(ii) bank(iii) bank(iv) boot parameter/main main main main vil x locked locked locked locked locked deep power down mode vih unlocked unlocked unlocked unlocked unlocked all blocks unlocked locked locked all blocks locked(valid to operate software lock release) write protection provided notes bank(i) locked locked locked rp# wp# vih vil "1" "0" s.r. 7 (dq7) write state machine status ready busy s.r. 6 (dq6) suspend status suspended operation in progress/completed s.r. 5 (dq5) erase status error successful s.r. 4 (dq4) program status error successful s.r. 3 (dq3) block status after erase error successful s.r. 2 (dq2) reserved - - s.r. 1 (dq1) reserved - - s.r. 0 (dq0) reserved - - symbol (i/o pin) status definition
rev.0.1_48a_bezz 14 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory min. typ. 1) max. ili input leakage current -1.0 +1.0 a ilo output leakage current -10 +10 a isb3 5 25 a 5mhz 20 30 ma 1mhz 4 8 ma vil input low voltage -0.5 0.4 v vih input high voltage 2.4 vcc+0.5 v vol output low voltage 0.45 v voh1 0.85xvcc v voh2 vcc-0.4 v vlko low vcc lock out voltage 2) 1.5 2.2 v symbol parameter test conditions limits isb2 vcc= 3.6v, vin= gnd/vcc, ce#= rp#= vcc 0.3v 0.1 vcc stand by current 6 a units 0v < vin < vcc 0v < vout < vcc 6 a isb4 vcc= 3.6v, vin= gnd or vcc, rp#= gnd 0.3v 0.1 vcc deep power down current vcc= 3.6v, vin= vil/vih, rp#= vil 5 10 icc1 vcc read current for word / byte icc1p vcc page read current vcc = 3.6v, vin = vil/vih, rp# = oe# = we# = vih, ce# =vil, iout = 0ma vcc = 3.6v, vin = vil/vih, rp# = oe# = we# =vih, ce# = vil, iout = 0ma ma icc2 vcc write current for word / byte vcc = 3.6v, vin = vil/vih, rp# = oe# = vih, ce# = we# = vil 15 ma 5mhz icc3 vcc program current vcc = 3.6v, vin = vil/vih, ce#= rp# = vih 35 ma icc4 vcc erase current vcc = 3.6v, vin = vil/vih, ce#= rp# = vih 35 ma icc5 vcc suspend current vcc = 3.6v, vin = vil/vih, ce#= rp# = vih 200 a iol = 4.0ma output high voltage ioh = -2.0ma ioh = -100ua device id code absolute maximum ratings dc electrical characteristics a0 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 hex. data manufacturer code vil "0" "0" "0" "1" "1" "1" "0" "0" 1ch device code (top boot) vih "0" "0" "1" "1" "1" "0" "0" "0" 38h device code (bottom boot) vih "0" "0" "1" "1" "1" "0" "0" "1" 39h code pins ( ta= - 40 ~85 c and flash vcc=3.0v~3.6v, unless otherwise noted) in the case of word mode, the output of upper byte data (dq15 - dq8) is ? 0h ? . 1) minimum dc voltage is ? 0.5v on input / output pins. during transitions, the level may u ndershoot to ? 2.0v for periods <20ns. maximum dc voltage on input / output pins is vcc+0.5v w hich, during transitions, may overshoot to vcc+1.5v for periods <20ns. all currents are in rms unless otherwise noted. 1) typical values at flash vcc=3.3v, ta=25 c . 2) to protect against initiation of write cycle during flash vcc power up / down, a write cycle is locked out for flash vcc less than vlko. if flash vcc is less than vlko, write state machine is rese t to read mode. when the write state machine is in busy state, i f flash vcc is less than vlko, the alteration of memory contents ma y occur. symbol parameter conditions min. max. units vcc vcc voltage -0.2 4.6 v vi1 all input or output voltage 1) -0.6 4.6 v ta ambient temperature -40 85 c tbs temperature under bias -50 95 c tstg storage temperature -65 125 c iout output short circuit current 100 ma with respect to gnd
rev.0.1_48a_bezz 15 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory ac electrical characteristics ( ta= - 40 ~85 c and flash vcc=3.0v~3.6v, unless otherwise noted) - timing measurements are made under ac waveforms for read operati ons. read only mode min. typ. max. trc tavav read cycle time 70 ns ta(ad) tavqv address access time 70 ns ta(ce) telqv chip enable access time 70 ns ta(oe) tglqv output enable access time 30 ns ta(pad) page read access time (after 2nd access) 25 ns tceph ce# "h"pulse width 30 ns tclz telqx chip enable to output in low-z 0 ns tdf(ce) tehqz chip enable high to output in high-z 25 ns tolz tglqx output enable to output in low-z 0 ns tdf(oe) tghqz output enable to high to output in high-z 25 ns tphz tplqz rp# low to output high-z 150 ns ta(byte) tfl/hqv byte# access time 70 ns tbhz tflqz byte# low to output high-z 25 ns toh toh output hold from ce#, oe# and address 0 ns tbcd telfl/h ce# low to byte# high or low 5 ns tbad tavfl/h address to byte# high or low 5 ns toeh twhgl oe# hold from we# high 10 ns tps tphel rp# recovery to ce# low 150 ns symbol parameter limits units flash vcc=3.0-3.6v
rev.0.1_48a_bezz 16 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory read / write mode (ce# control) ac electrical characteristics ( ta= - 40 ~85 c and flash vcc=3.0v~3.6v, unless otherwise noted) read / write mode (we# control) - read timing parameters during command write operations mode are the same as during read only operation mode. - typical values at flash vcc=3.3v and ta=25 c . min. typ. max. twc tavav write cycle time 70 ns tas tavwh address setup time 35 ns tah twhax address hold time 0 ns tds tdvwh data setup time 35 ns tdh twhdx data hold time 0 ns toeh twhgl oe# hold from we# high 10 ns tcs telwl chip enable setup time 0 ns tch twheh chip enable hold time 0 ns twp twlwh write pulse width 35 ns twph twhwl write pulse width high 30 ns tbs tfl/hwh byte enable high or low set-up time 50 ns tbh twfl/h byte enable high or low hold time 70 ns tghwl tghwl oe# hold to we# low 0 ns tbls tphhwh block lock setup to write enable high 70 ns tblh tqvph block lock hold from valid srd 0 ns tdap twhrh1 duration of auto program operation(byte mode) 30 300 s tdap twhrh1 duration of auto program operation(word mode) 30 300 s tdap twhrh1 duration of auto program operation(page mode) 4 80 ms tdae twhrh2 duration of auto block erase operation 150 600 ms twhrl twhrl delay time during internal operation 70 ns tps tphwl rp# recovery to we# low 150 ns symbol parameter limits units flash vcc=3.0-3.6v - timing measurements are made under ac waveforms for read operati ons. - typical values at flash vcc=3.3v and ta=25 c . min. typ. max. twc tavav write cycle time 70 ns tas taveh address setup time 35 ns tah tehax address hold time 0 ns tds tdveh data setup time 35 ns tdh tehdx data hold time 0 ns toeh tehgl oe# hold from ce# high 10 ns tws twlel write enable setup time 0 ns twh tehwh write enable hold time 0 ns tcep teleh ce# pulse width 35 ns tceph tehel ce#"h" pulse width 30 ns tbs tfl/heh byte enable high or low set-up time 50 ns tbh tehfl/h byte enable high or low hold time 70 ns tghel tghel oe# hold to ce# low 0 ns tbls tphheh block lock setup to chip enable high 70 ns tblh tqvph block lock hold from valid srd 0 ns tdap tehrh1 duration of auto program operation(byte mode) 30 300 s tdap tehrh1 duration of auto program operation(word mode) 30 300 s tdap tehrh1 duration of auto program operation(page mode) 4 80 ms tdae tehrh2 duration of auto block erase operation 150 600 ms tehrl tehrl delay time during internal operation 70 ns tps tphel rp# recovery to ce# low 150 ns symbol parameter limits units flash vcc=3.0-3.6v
rev.0.1_48a_bezz 17 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory during power up / down, by the noise pulses on control pins, the device has possibility of accidental erase of programming. the device must be protected against initiation of write cycle f or memory contents during power up / down. the delay time of min. 2 sec is always required before read operation or write operation is initiated from the time flash vcc reaches flash vcc min. during power up /down. by holding rp#=vil, the co ntents of memory is protected during flash vcc power up / down. during power up, rp# must be held vil for min. 2 s from the time flash vcc reaches flash vcc min.. during power down, rp# must be held vil until flash vcc reaches gnd. rp# doesn ? t have latch mode, therefore rp# must be held vih during read operation or erase / program operat ion. parameter min. typ. max. units block erase time 150 600 ms main block write time (byte mode) 2 8 sec main block write time (word mode) 1 4 sec page write time 4 80 ms flash to page buffer time 100 150 s parameter min. typ. max. unit program susupend time 15 s erase susupend time 15 s symbol parameter min. typ. max. unit tvcs rp#=vih setup time from flash vcc min. 2 s flash vcc power up / down timing program suspend / erase suspend time program / erase time
rev.0.1_48a_bezz 18 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory flash vcc power up / down timing ac waveforms for read operation and test conditions t ps 3.0v gnd v cc v ih rp# read /write inhibit t vcs ce# we# read /write inhibit v il v ih v il v ih v il t ps read /write inhibit test conditions for ac characteristics input voltage : v il =0v, v ih =flash vcc input rise and fall times : < 5ns reference voltage at timing measurement : (flash vcc)/2 output load : 1 ttl gate + cl(30pf) or output valid a 20 -a 0 (word) a 20 -a -1 (byte) ce# oe# we# data address valid high-z dut 3.3kohm 1n914 1.3v cl=30pf rp# v ih v il t a(ad) t a(ce) v ih v il v ih v il t df(ce) t df(oe) v ih v il t oeh t a(oe) t oh high-z t olz t clz t phz v oh v o v ih v il t ps t rc t ceph ffh cl=30pf - after inputting read array command ffh, it is necessary to make ce# ? h ? pulse more than 30ns (tceph). and after inputting read array command ffh, it is also necessa ry to keep 30ns to recover before starting read after we# rises ? h ? in case of changing address(es) and ce#= ? l ? .
rev.0.1_48a_bezz 19 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory ac waveforms for page read operation byte ac waveforms for read operation address a20-a0 ce# oe# byte# data d7-d0 address valid high-z v ih v il t a(ad) t a(ce) v ih v il v ih v il t df(ce) t df(oe) v ih v il t a(oe) output valid t oh t olz t clz v oh v ol t a(byte) t bcd t bad data d14-d8 v oh v ol high-z t bad t a(byte) t bhz t a(ad) valid valid valid d15/a-1 address valid v ih v il d15 a-1 address valid when byte# = vih, ce# = oe# = vil, d15/a - 1 is output status. at this time, input signal must not be appl ied. a 20 - a 2 v ih v il 1st address ce# v ih v il we# v ih v il v ih v il high-z data f3h page address valid v ih v il a 1 - a 0 (word) a 1 - a -1 (byte) address t a(ce) address valid (voluntary address) oe# v ih v il t a(ad) t a(oe) t a(oe) valid t a(pad) t a(pad) t a(pad) 2nd ~ nth t ceph valid valid valid - after inputting page read command f3h, it is necessary to make c e# ? h ? pulse more than 30ns ( tceph ). and after inputting page read command f3h, it is also necessar y to keep 30ns to recover before starting read after we# rises ? h ? in case of changing address( es ) and ce#= ? l ? . - once page read mode is valid, the mode is kept until rp# is set to vil or the chip is powered off. - word mode(byte#=vih):n=4, byte mode(byte#=vil):n=8
rev.0.1_48a_bezz 20 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory ac waveforms for word / byte program operation (we# control) ac waveforms for word / byte program operation (ce# control) address bank address v ih v il valid address valid program read status register write read array command bank address ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 40h din srd busy srd ready ffh v ih v il rp# v ih v il wp# t ps t cs t bls t ch t wp t wc t ah t as t oeh t whrl t dh t ds t dap t blh t a(oe) t a(ce) t wph v ih v il byte# t bs t bh a 20 -a -1 (byte) a 20 -a 0 (word) address bank address v ih v il valid address valid program read status register bank address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 40h din srd busy srd ready ffh v ih v il rp# v ih v il wp# t ps t ws t bls t wh t cep t wc t ah t as t oeh t ehrl t dh t ds t dap t blh t a(oe) t a(ce) write read array command v ih v il byte# t bs t bh a 20 -a -1 (byte) a 20 -a 0 (word)
rev.0.1_48a_bezz 21 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory ac waveforms for page program operation (we# control) ac waveforms for page program operation (ce# control) \ a 20 -a 7 bank address v ih v il valid address valid read status register write read array command bank address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 41h din dout srd busy ffh v ih v il rp# v ih v il wp# t ps t bls t wc t dap t blh the other bank address valid address valid v ih v il address 00h 01h-feh ffh valid din din srd ready t as t ah t cs t ch t wp t wph t dh t ds t oeh t a(ce) t a(oe) t ghwl t oeh t whrl t a(ce) t a(oe) a 6 -a -1 (byte) v ih v il byte# t bs t bh 00h 01h-7eh 7fh valid a 6 -a 0 (word) bank address valid bank address v ih v il valid address valid read status register write read array command bank address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 41h din dout srd busy ffh v ih v il rp# v ih v il wp# t ps t bls t wc t dap t blh the other bank address vaild address valid address valid v ih v il din din srd ready t as t ah t ws t wh t cep t ceph t dh t ds t oeh t a(ce) t a(oe) t ghel t oeh t ehrl t a(ce) t a(oe) a 20 - a 7 address v ih v il byte# t bs t bh 00h 01h-feh ffh valid a 6 -a -1 (byte) 00h 01h-7eh 7fh valid a 6 -a 0 (word) bank address valid
rev.0.1_48a_bezz 22 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory ac waveforms for erase operation (we# control) ac waveforms for erase operation (ce# control) address bank address v ih v il valid address valid erase read status register write read array command bank address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 20h d0h srd busy srd ready ffh v ih v il rp# v ih v il wp# t ps t cs t bls t ch t wp t wc t ah t as t oeh t whrl t dh t ds t dae t blh t a(oe) t a(ce) t wph v ih v il byte# t bh t bs a 20 -a -1 (byte) a 20 -a 0 (word) bank address valid address bank address v ih v il valid address valid erase read status register write read array command bank address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 20h d0h srd busy srd ready ffh v ih v il rp# v ih v il wp# t ps t ws t bls t wh t cep t wc t ah t as t oeh t ehrl t dh t ds t dae t blh t a(oe) t a(ce) v ih v il byte# t bh t bs a 20 -a -1 (byte) a 20 -a 0 (word) bank address valid
rev.0.1_48a_bezz 23 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory ac waveforms for word / byte program operation with bgo (we# con trol) ac waveforms for word / byte program operation with bgo (ce# con trol) v ih v il address valid program read status register read array in another bank ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 40h din srd busy t cs t ch t wp t wc t ah t as t oeh t whrl t ds t a(oe) t a(ce) t wph address a 20 - a 7 bank address v ih v il valid address valid address valid program in one bank change bank address address valid address valid address valid dout dout t dh a 6 -a -1 (byte) a 6 -a 0 (word) v ih v il address valid program ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 40h din srd busy t ws t wh t cep t wc t ah t as t oeh t ehrl t dh t ds t a(oe) t a(ce) read status register read array in another bank bank address v ih v il valid address valid address valid program in one bank change bank address address valid address a 20 - a 7 address valid address valid dout dout a 6 -a -1 (byte) a 6 -a 0 (word)
rev.0.1_48a_bezz 24 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory ac waveforms for page program operation with bgo (we# control) ac waveforms for page program operation with bgo (ce# control) \ a 20 -a 7 bank address v ih v il valid address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 41h din srd busy t wc v ih v il address din din t as t ah t cs t ch t wp t wph t dh t ds t oeh t whrl t a(ce) t a(oe) read array in another bank address valid change bank address address valid address valid address valid program in one bank dout dout 00h 01h-feh ffh a 6 -a -1 (byte) 00h 01h-7eh 7fh a 6 -a 0 (word) v ih v il ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 41h din srd busy t wc t dap v ih v il din din t as t ah t ws t wh t cep t ceph t dh t ds t oeh t ehrl t a(ce) t a(oe) a 20 - a 7 address bank address valid address valid read array in another bank address valid change bank address address valid program in one bank dout dout 00h 01h-feh ffh a 6 -a -1 (byte) 00h 01h-7eh 7fh a 6 -a 0 (word)
rev.0.1_48a_bezz 25 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory ac waveforms for erase operation with bgo (we# control) ac waveforms for erase operation with bgo (ce# control) address bank address v ih v il valid address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 20h d0h srd busy t ws t wh t cep t wc t ah t as t oeh t ehrl t dh t ds t a(oe) t a(ce) dout dout address valid address valid read array in another bank read status register program in one bank change bank address a 20 -a 0 (word) a 20 -a -1 (byte) address bank address v ih v il valid address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data 20h d0h srd busy t cs t ch t wp t wc t ah t as t oeh t whrl t dh t ds t a(oe) t a(ce) t wph dout dout address valid address valid read status register read array in another bank program in one bank change bank address a 20 -a -1 (byte) a 20 -a 0 (word)
rev.0.1_48a_bezz 26 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory ac waveforms for suspend operation (we# control) ac waveforms for suspend operation (ce# control) address v ih v il bank address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data b0h srd valid v ih v il rp# v ih v il wp# t cs t ch t wp t ah t as t oeh suspend time t blh t a(oe) t a(ce) bank address valid s.r.6,7=1 read status register a 20 -a 0 (word) a 20 -a -1 (byte) address v ih v il bank address valid ce# v ih v il oe# v ih v il we# v ih v il v ih v il high-z data b0h srd valid v ih v il rp# v ih v il wp# t ah t as t oeh suspend time t blh t a(oe) t a(ce) bank address valid s.r.6,7=1 read status register t ws t wh t cep a 20 -a 0 (word) a 20 -a -1 (byte)
rev.0.1_48a_bezz 27 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory word / byte program flow chart block erase flow chart page program flow chart status register check flow chart start write 40h write address, data status register read sr.7 = 1? full status check if desired word / byte program completed write b0h? no yes no suspend loop write d0h yes yes start write 41h n = 0 write address n, data n sr.7 = 1? full status check if desired page program completed write b0h? no yes no suspend loop write d0h yes yes n + 1 n = 7fh? n = ffh? no yes status register read start write 20h write d0h block address sr.7 = 1? full status check if desired erase completed write b0h? no yes no suspend loop write d0h yes yes status register read start sr.3 = 0? no yes sr.4,5 = 1? no yes sr.5 = 0? no yes sr.4 = 0? no yes pass (block erase, program) command sequence error block erase error program error (page program) block erase error (block fail)
rev.0.1_48a_bezz 28 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory single data load to page buffer flow chart suspend / resume flow chart clear page buffer flow chart page buffer to flash flow chart start write 74h write address, data load finished? single data load to page buffer completed no yes start write b0h status register read s.r. 7=1? no yes write ffh read array data read finished? operation restart no yes s.r. 6=1? no yes write d0h erase/ program finished suspend resume start write 0eh write d0h page address sr.7 = 1? full status check if desired page buffer to flash completed write boh? no yes no suspend loop write d0h yes yes status register read start write 55h write d0h clear page buffer completed
rev.0.1_48a_bezz 29 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory operation status (wp#=vih) 1) in case of page read, f3h is used instead of ffh in operation st atus (wp#=vih). 2) once page read mode is set, page read mode is kept until powe r off or rp# is set to vil. 3) after setting up clear page buffer, d0h enables to clear page buffer. 4) to access any bank during erase all unlocked block results s tatus register read. although read status register command and read array command can be issued under suspend state, output data make no sense. read status register ffh ffh 90h read/standby state (random read mode) 70h clear status register 50h read array (random read) change bank address erase all unlocked blocks setup block erase setup word program setup page program setup page buffer to flash setup flash to page buffer setup single data load to page buffer setup clear page buffer setup d0h 55h 74h wd f1h 0eh 41h 40h a7h erase & verify read status register program & verify read status register d0h wdi i=0-127 wd d0h setup state internal state d0h ready read status register suspend state d0h d0h b0h b0h other others 90h 70h 20h read array (random read) read device identifier read array (random read) ffh 70h others 3) d0h change bank address read state with bgo change bank address read array (random read) read array (random read) read state with bgo back bank read state
rev.0.1_48a_bezz 30 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory operation status (wp#=vil) 1) in case of page read, f3h is used instead of ffh in operation st atus (wp#=vil). 2) once page read mode is set, page read mode is kept until powe r off or rp# is set to vil. 3) ba, ba#: block address, block address# (shown in command list (wp#=vil) in detail). 4) after setting up clear page buffer, d0h enables to clear page buffer. change bank address read status register ffh ffh 90h read/standby state (random read mode) 70h clear status register 50h read array (random read) change bank address block erase setup word program setup page program setup page buffer to flash setup flash to page buffer setup single data load to page buffer setup clear page buffer setup d0h 55h 74h wd f1h 0eh 41h 40h erase & verify read status register program & verify read status register d0h wdi i=0-127 wd d0h setup state internal state ready 70h read status register suspend state d0h d0h b0h b0h read state with bgo other other 90h 70h 20h read array (random read) read device identifier change bank address read array (random read) ffh read array (random read) software lock release setup software lock release setup software lock release setup software lock release setup software lock release setup others 60h ba 3) ach ba# 3) 7bh others others others 4) others d0h read array (random read) read state with bgo back bank read state read array (random read) change bank address
rev.0.1_48a_bezz 31 m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory package dimension 52 ptg - a e y b m x d z z 1 detail g detail f a a 2 1 c a 3 l 1 l lp h e e g a f m e e i 2 b 2 eiaj package code jedec code weight(g) lead material alloy 42 tsopii52-p-350-0.40 scale: 3.5/1 recommended mount pad 52 27 1 26 symbol dimension in millimeters min. nom. max. a a 1 a 2 b c d e e h e l l 1 l p a3 z z 1 x y m e i 2 b 2 1.2 0.2 0.27 0.175 10.89 8.99 10.69 0.65 0.75 0.55 0.08 0.1 10 0.225 0.9 0 0.4 0.25 0.45 0.6 0.8 0.5 0.45 10.49 10.29 0.4 8.89 8.79 10.79 10.69 0.105 0.125 0.12 0.17 1.0 0.05 0.125 9.09 theta theta
these materials are intended as a reference to assist our custom ers in the selection of the renesas technology corporation product best suited to the customer's ap plication; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. renesas technology corporation assumes no responsibility for any damage , or infringement of any third - party's rights, originating in the use of any product data, diag rams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents infor mation on products at the time of publication of these materials , and are subject to change by renesas technology corporation without notice due to product improvemen ts or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product informati on before purchasing a product listed herein. the information described here may contain technical inaccuracie s or typographical errors. renesas technology corporation assumes no responsibility for any damage , liability, or other loss rising from these inaccuracies or err ors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page ( http://www.renesas.com ). when using any or all of the information contained in these mate rials, including product data, diagrams, charts, programs, and a lgorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage , liability or other loss resulting from the information contain ed herein. renesas technology corporation semiconductors are not designed or manuf actured for use in a device or system that is used under circums tances in which human life is potentially at stake. please conta ct renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, su ch as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese ex port control restrictions, they must be exported under a license from the japanese government and cannot be imported into a coun try other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan an d/or the country of destination is prohibited. please contact renesas technology corporation for further details on these materials o r the products contained therein. renesas technology corporation puts the maximum effort into making semi conductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage.remember to give due co nsideration to safety when making your circuit designs, with app ropriate measures such as (i) placement of substitutive, auxilia ry circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials keep safety first in your circuit designs! rej03c0235 ? 2003 renesas technology corp. new publication, effective april 2003. specifications subject to change without notice nippon bldg.,6 - 2, otemachi 2 - chome, chiyoda - ku ,tokyo,100 - 0004 japan m5m29kb/t331atp renesas lsis preliminary notice: this is not a final specification. some parametric limits are subject to change. 33,554,432 - bit (4,194,304 - word by 8 - bit /2,097,152 - word by 16 - bit) cmos 3.3v - only, block erase flash memory

▲Up To Search▲

Price & Availability of M5M29KB331ATP

	To Download M5M29KB331ATP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .